When recording digital signals, such as digital speech signals, digital video signals or data, error correction code data is first appended to the digital signals, and the resulting data is routed to a modulating circuit where it is converted by channel coding into the code suited to the characteristics of a recording/reproducing system.
An optical disc, such as, a compact disc (CD), is a recording medium having a wide field of application as a package medium for picture information or as a storage device for a computer. The optical disc system reproduces signals recorded on a reflective surface of the disc via a transparent substrate having a thickness of the order of 1.2 mm. On the optical disc, information such as digitized audio signals, video signals or digital data, is recorded. In this case, the error correction code data is appended to the digital signals, and the resulting data is routed to a modulating circuit where it is converted by so-called channel coding into code data suited to the characteristics of the recording/reproducing system.
The signal format of the above-mentioned compact disc (CD) system is summarized as follows:
______________________________________ sampling frequency 44.1 kHz number of quantizing bits 16 (linear) modulation system EFM channel bit rate 4.3218 Mb/s error correction system CIRC data transmitting rate 2.034 Mb/s ______________________________________
The modulation system employed is 8-14 conversion or EFM.
With the EFM, an input 8-bit code, referred to hereinafter as a symbol, is converted into a 14 channel bit code, to which a frame synchronization signal of 24 channel bits and a subcode of 14 channel bits are appended and the neighboring codes are interconnected by merging bits of 3 channel bits. The resulting data is recorded by the NRZI modulation system.
FIG. 1 shows a frame structure of the CD system.
Referring to FIG. 1, 24 symbol data (music signals) and 8 symbol parity, entering a modulating circuit from a cross-interleave Reed-Solomon code (CIRC) encoder during a sync frame (6 sample value domains, six samples each of the L and R channels, with each sample being 16-bit data) are transformed into 14 channel bits and connected by merging bits of three channel bits to give 588 channel bits per frame. The resulting data is recorded by the NRZI system at a channel bit rate of 4.3218 Mbps.
The respective symbols entering the modulating circuit are transformed, with reference to a lookup table composed of a ROM, into a channel bit pattern in which the number of "0"s between "1" and "1" is not less than 2 and not more than 10. The channel bit pattern of a frame synchronization signal Sf is "100000000001000000000010" in binary expression. As for the merging bit pattern, one of "000", "001", "010" and "100" is selected. Each sub-coding frame is made up of 98 frames. As the subcode for the 0'th and first frames, the subcode sync signal S0 (="00100000000001") and S1 (="00000000010010") are appended (see FIG. 2).
FIG. 3 shows, for a typical sample value of input data, a channel bit pattern after EFM and a digital sum variation (DSV).
Each 16-bit sample is split into upper 8 bits and lower 8 bits each of which is entered to the modulation circuit via a CIRC encoder for 8-14 conversion to produce 14 channel-bit information bits. Not less than 2 and not more than 10 "0 "s are interposed between "1" and "1" of the information bits, as previously described. One of the merging bits "000", "001", "010" and "100" is selected. This rule is observed at all times at the connecting portions of the 14 information bits, so that EFM signals based on 17-channel bits are generated and outputted from the modulating circuit at 4.3218 Mbps. The number of channel bits is 27 in the case of the frame synchronization signal Sf.
Since not less than 2 and not more than 10 channel bits are interposed between an optional channel bit "1" and the next channel bit "1", the period during which the high level or the low level of the NRZI recording waveform continues, that is the recording wavelength, is necessarily not less than 3 T and not more than 11 T (see FIG. 3).
In this case, the shortest recording wavelength is 3 T and the longest recording wavelength is 11 T, with T being a period of a channel clock of 4.3218 MHz. This is referred to hereinafter as the 3 T.about.11 T rule of the EFM modulation regulation.
The digital sum value or variation (DSV) is now considered as an index of the dc balance of the NRZI recording waveform. The DSV is given as a time integral of the recording waveform. That is, the variant of the DSV when the high level of the recording waveform has continued for a unit time T is +1, while the variant of the DSV when the low level of the recording waveform has continued for a unit time T is -1.
The time change of DSV when the initial value of DSV at time t.sub.0 is assumed to be zero is given at the lower most portion of FIG. 3. The modulated signal during the time since t.sub.1 until t.sub.2 is not uniquely determined by the 17-channel bit pattern "01000001000001001", but depends on the modulated signals level at time t.sub.1, that is on the ultimate level of the modulated signal waveform during the time interval from time t.sub.0 until time t.sub.1 (referred to hereinafter as CWLL).
Thus the modulated signal waveform illustrated is that for the CWLL at time t.sub.0 being at a low level (CWLL="0"). The modulated signal waveform for CWLL="1" (high level) is inverted from the pattern for CWLL="0" so that the high and low levels are inverted to low and high levels, respectively.
Similarly, the DSV is also increased or decreased depending upon the CWLL, such that, if CWLL="0" at time t.sub.0, the DSV variant with the information pattern "01000100100010" (referred to hereinafter as 14 NWD), that is the DSV variant during the time period from t.sub.0 until t.sub.0 +14, is +2, as shown in FIG. 3. Conversely, if CWLL="1" at time t.sub.0, 14 NWD=-2. The DSV variant since time t.sub.0 +14 until t.sub.1 +14 is referred to as 17 NWD.
The merging bits, inserted since time t.sub.0 +14 until time t.sub.1, is now explained. Of the four margin bits "000", "001", "010" and "100", "001" or "100" cannot be inserted under the above-mentioned 3 T.about.11 T rule, such that only "010" or "000" can be inserted. That is, if the number of "0"s at the trailing end of the previous information bit pattern, outputted before the merging bit, is B, and the number of "0"s at the leading end of the subsequently outputted current information bit pattern is A, since B=1 and A=1, the leading and trailing ends of the merging bit must be "0" and "0", such that the merging bit pattern that can be inserted becomes "0X0", where X is arbitrary (don't care).
In the lower most portion of FIG. 3, there is shown the DSV with the bits "010" inserted as merging bits, by a solid line, while there is shown the DSV with the bits "000" inserted as merging bits, by a broken line.
In general, the merging bits to be inserted at a connecting point need to be selected so that the 3 T.about.11 T rule of the modulation regulation will be met. Similarly, such merging bits are prohibited which, when inserted, will produce a repetition by two times of a 11 T pattern which is the same as the 11 T frame synchronization pattern.
Of the merging bits satisfying the above requirements, such merging bits are selected as optimum merging bits which, when inserted, will produce the smallest absolute value of the cumulative DSV from the merging bit until the end of the next information bit pattern connected to the prevailing cumulative DSV.
In the example of FIG. 3, the DSV at time t.sub.1 +14 when the merging bits "010" are inserted is +3, while the DSV at the same time point when the merging bits "000" are inserted is -1, so that the merging bits "000" are selected.
The merging bits, found by the above-described algorithm, satisfy the 3 T.about.11 T rule of the modulation regulation at the connecting portion between two 14-bit data, while prohibiting generation of an erroneous frame sync signal and approaching the cumulative DSV of the EFM signal to a value as close to zero as possible.
Meanwhile, with the conventional EFM system, since the shortest run-length is limited to two, two merging bits suffice if for the purpose of coping with run-length limitations. If the number of the merging bits can be reduced to two, the data recording density may be increased by a factor of 17/16 without altering the physical size such as the recording wavelength.
However, there are only three sorts of the 2-bit merging bits. In addition, it is a frequent occurrence that only one of the three sorts of the merging bits can be inserted because of limitations such as those imposed by run-length. Thus, with the conventional DSV control system, there exist a large number of domains in which it is impossible to control the DSV. Consequently, low-frequency components of the modulated signals cannot be sufficiently suppressed to affect servo stability or the data error rate on data demodulation.
In view of the foregoing, it is a principal object of the present invention to provide a signal modulating method, a signal modulating apparatus, a signal demodulating method and a signal demodulating apparatus whereby the input M bits, such as an input 8-bit code string, is directly transformed into N-channel bits, such as 16 channel bits, without employing the above-mentioned merging bits at the time of signal modulation, thereby reducing ill effects on the DSV control and also enabling sufficient suppression of the low-frequency components.